The widespread of smart consumer electronic devices of which we are in incessant contact with in our daily lives has boosted huge market opportunities in recent times. One of the common features of these smart devices lies in their ability to instantly capture digital images of objects of interest. At present, this imaging capability is achieved via an integrated complementary metal oxide semiconductor (CMOS) image sensor, which is essentially made up of an array of minute optically sensitive electronic elements (p-n semiconductor junctions or photodiodes). The captured image is then transferred and stored in an on-board memory chip for further manipulation. Here, the NAND flash memory is also made up of an array of electronic elements called floating gate transistor. For both the sensor and memory components, information is represented in terms of either the absence or presence of electronic charges. The primary success of the CMOS image sensor and NAND flash memory technologies hinges on the use of well-established CMOS fabrication processes, which allow for integration of the image sensor and memory circuits, along with other control circuits on a given chip at a relatively low cost. Moving forward, the current technologies are unlikely to fulfill the future need for higher resolution image sensing devices. This is because the quantity of charges that individual sensor and memory components can store is fast reducing as their dimensions are being scaled down to achieve higher sensing resolution and storage capacity. With minimal charge storage, the loss of charges can induce substantial parameter variability issues and shrink the program/erase memory window beyond the acceptable range. In addition, due to the large difference in aspect ratios of the sensing and memory elements, direct on-chip integration of the image sensor and NAND flash memory circuits cannot usually be achieved. With integration made at the component level, the overall operating speed is limited by the external data buses.